`timescale 1ns / 1ps

module EX_MEM(
    input clk,
    input reset,
    input [31:0] E_AO,
    input [31:0] E_V2,
    input [31:0] E_PC,
    input [2:0] E_RinSel,
    input E_RegWr,
    input E_MemWr,
    input [4:0] E_A1,
    input [4:0] E_A2,
    input [1:0] E_Tu1,
    input [1:0] E_Tu2,
    input [4:0] E_A3,
    input [1:0] E_Tn,    
    input [1:0] E_store,
    input [2:0] E_Dop,
    input [31:0] E_MDV,
    input E_ld,
    input E_st,
    input [31:0] E_instr,
    input E_CP0Wr,
    input E_eret,
    input E_isBD,
    output reg [31:0] M_AO,
    output reg [31:0] M_V2,
    output reg [31:0] M_PC,
    output reg [2:0] M_RinSel,
    output reg M_RegWr,
    output reg M_MemWr,
    output reg [4:0] M_A1,
    output reg [4:0] M_A2,
    output reg [1:0] M_Tu1,
    output reg [1:0] M_Tu2,
    output reg [4:0] M_A3,
    output reg [1:0] M_Tn,
    output reg [1:0] M_store,
    output reg [2:0] M_Dop,
    output reg [31:0] M_MDV,
    output reg M_ld,
    output reg M_st,
    output reg [31:0] M_instr,
    output reg M_CP0Wr,
    output reg M_eret,
    output reg M_isBD
    );

    initial begin
        M_AO <= 0;
        M_V2 <= 0;
        M_PC <= 0;
        M_RinSel <= 0;
        M_RegWr <= 0;
        M_MemWr <= 0;
        M_A1 <= 0;
        M_A2 <= 0;
        M_Tu1 <= 0;
        M_Tu2 <= 0;
        M_A3 <= 0;
        M_Tn <= 0;    
        M_store <= 0;    
        M_Dop <= 0;
        M_MDV <= 0;
        M_ld <= 0;
        M_st <= 0;
        M_instr <= 0;
        M_CP0Wr <= 0;
        M_eret <= 0;
        M_isBD <= 0;
    end

    always @(posedge clk) begin
        if(reset) begin
            M_AO <= 0;
            M_V2 <= 0;
        //    M_PC <= 0;
            M_RinSel <= 0;
            M_RegWr <= 0;
            M_MemWr <= 0;
            M_A1 <= 0;
            M_A2 <= 0;
            M_Tu1 <= 0;
            M_Tu2 <= 0;
            M_A3 <= 0;
            M_Tn <= 0;     
            M_store <= 0;    
            M_Dop <= 0;
            M_MDV <= 0;
            M_ld <= 0;
            M_st <= 0;
            M_instr <= 0;
            M_CP0Wr <= 0;
            M_eret <= 0;
            M_isBD <= 0;
        end
        else begin
            M_AO <= E_AO;
            M_V2 <= E_V2;
            M_PC <= E_PC;
            M_RinSel <= E_RinSel;
            M_RegWr <= E_RegWr;
            M_MemWr <= E_MemWr;
            M_A1 <= E_A1;
            M_A2 <= E_A2;
            M_Tu1 <= E_Tu1;
            M_Tu2 <= E_Tu2;
            M_A3 <= E_A3;
            M_Tn <= (E_Tn == 0) ? 0 : (E_Tn - 1);     
            M_store <= E_store;    
            M_Dop <= E_Dop;
            M_MDV <= E_MDV;
            M_ld <= E_ld;
            M_st <= E_st;
            M_instr <= E_instr;
            M_CP0Wr <= E_CP0Wr;
            M_eret <= E_eret;
            M_isBD <= E_isBD;
        end
    end

endmodule
